This invention relates to integrated circuits and, more particularly, to circuitry that performs floating-point operations on an integrated circuit.
Floating-point numbers are commonplace for representing real numbers in scientific notation in integrated circuits thanks to a desirable balance between numeric range and precision. Floating-point numbers are typically represented in binary format in accordance with the IEEE754 standard, which defines a floating-point number as consisting of a sign, a mantissa, and an exponent.
Elementary operations such as the natural exponential function or the natural logarithmic function are frequently performed on floating-point numbers. The implementation of these operations in digital circuits often use polynomial approximation methods that combine small tables and branching with arithmetic floating-point operation such as addition, subtraction, and multiplication.
However, polynomial approximation methods of elementary operations often require a large amount of latency and use many device resources. Therefore, a more efficient support for elementary operations such as the natural exponential function and the natural logarithmic function and similarly resource intensive floating-point operations may be desirable.